Principal Engineer/ Senior Engineer/ Engineer, Digital Design Verification

Ref: umec20200203


  • Research and development in digital IC implementation for machine learning and/or deep neural network applications;
  • Develop test methodology and test plans based on logic design specifications;
  • Module level and/or top level verification for SoC system;
  • Independently handle test environment set up;
  • Test case creation/generation and code coverage analysis.


  • Bachelor’s Degree in Computer Engineering/Electrical Engineering/Information Engineering or related fields with 6+ years’ experience, or Master’s Degree with 3+ years’ experience, or PhD holder in related area. Candidates with less experience will be considered position of Engineer;
  • Proficient in Verilog and SystemVerilog languages;
  • Familiar with verification methodology, such as UVM or OVM;
  • Familiar with Perl/Python/Makefile scripting is a plus;
  • Strong problem analyzing & solving, good communication skill & team work.

How to apply?

Interested parties please send your application to by quoting reference number with detailed resume including current and expected salary by email. Only short-listed candidates will be contacted.

All data provided will be kept in strict confidence and will be used for employment related purpose.